Design of Processors
Design and Simulation of a 6-stage pipelined microprocessor and multicycle microprocessor
Guide: Prof. Virendra Singh, IIT Bombay.
- Designed a Six-Stage Pipelined processor, which was optimized for performance using hazard mitigation and a Multi-cycle processor with a given RISC ISA
- Designed a Lookup Table for branch prediction and a feed-forward logic to increase the throughput of the pipelined processor for a wide variety of instruction combinations
- Implemented the complete design of the two processors on VHDL using Quartus Prime and verified the performance for a complex set of instructions
